Many different output buffer circuits have been used in the prior art. A pipelined output buffer circuit is also known in the prior art. In a pipelined output buffer circuit, data is held in the output register from the previous cycle and then clocked out on the rising edge of a clock. Typical prior art output buffers include two latch circuits in series having the output terminal of the first latch circuit connected to the input terminal of the next latch circuit. The output terminal of the second latch circuit is connected to the input of the output driver.
In the traditional configuration as described above, the two series latches from the data input to the data output form a D-flipflop. When the control ling clock is in a first state, data is transferred into the first latch circuit. When the clock transitions to a second phase, data is clocked to the output and the input terminal is placed in a high impedance mode. On subsequent clock cycles, data is clocked into the first latch circuit on the first phase of the cycle and clocked out of the latch circuit on the second phase of the cycle.
The data output by such an output buffer circuit is the true data provided at the input delayed by one clock cycle.
Such an output buffer is adequate for many prior art uses. However, it suffers from a number of severe drawbacks. First, such an output buffer is limited in speed because data can only be transferred over one entire clock cycle. The new data is not presented to the output terminal until the full completion of the clock cycle. Therefore, the circuit operation is slower than would be desired.
The two flipflops are connected in series as a master latch driving a slave latch. The master latch is set on one edge of the clock pulse and sets the slave latch on the subsequent edge of the clock pulse. The data is output at the output terminal of the slave latch.